I am the head of a hardware acceleration team at ByteDance’s System Department, overseeing a diverse range of hardware-software co-design initiatives that aim to accelerate networking, compute, storage, and security for the cloud and AI systems.
Before that, I was an expert engineer at Tencent. I launched Tencent’s SmartNIC/DPU project as the founding manager, and led the cloud network development team in the network platform department of the Technology and Engineering Group (TEG).
Prior to joining Tencent, I was a senior software engineer and tech lead in Azure Networking at Microsoft HQ, working as one of the few early core members on innovative projects including SmartNIC, RDMA, and Catapult FPGA. Before moving to Azure, I conducted research on data center networking and hardware acceleration, as part of the wireless and networking group at Microsoft Research Asia (MSRA).
I earned my Ph.D. in computer architecture from the Institute of Computing Technology (ICT), Chinese Academy of Science (CAS), co-advised by Prof. Gaogang Xie and Prof. Yingke Xie. I obtained my bachelor’s degree from the University of Science and Technology of China (USTC).
I have extensive experience in building and leading hardware acceleration teams that deliver innovative solutions at hyperscalers. My interests lie broadly in hardware-software co-design for the cloud and AI systems, with a recent focus on high-speed networking, AI interconnects, and domain-specific accelerators. My research has been published in top-tier networking and system conferences such as SIGCOMM, NSDI & OSDI while many of my engineering efforts have been widely deployed in data centers.
If you are interested in collaborating or learning more about my work, please don’t hesitate to reach out to me!
Publications
- Zilong Wang, Layong Luo, Qingsong Ning, Chaoliang Zeng, Wenxue Li, Xinchen Wan, Peng Xie, Tao Feng, Ke Cheng, Xiongfei Geng, Tianhao Wang, Weicheng Ling, Kejia Huo, Pingbo An, Kui Ji, Shideng Zhang, Bin Xu, Ruiqing Feng, Tao Ding, Kai Chen, Chuanxiong Guo, SRNIC: A Scalable Architecture for RDMA NICs, USENIX NSDI, 2023.
- Chaoliang Zeng, Layong Luo, Qingsong Ning, Yaodong Han, Yuhang Jiang, Ding Tang, Zilong Wang, Kai Chen, Chuanxiong Guo, FAERY: An FPGA-accelerated Embedding-based Retrieval System, USENIX OSDI, 2022.
- Chaoliang Zeng, Layong Luo, Teng Zhang, Zilong Wang, Luyang Li, Wenchen Han, Nan Chen, Lebing Wan, Lichao Liu, Zhipeng Ding, Xiongfei Geng, Tao Feng, Feng Ning, Kai Chen, Chuanxiong Guo, Tiara: A Scalable and Efficient Hardware Acceleration Architecture for Stateful Layer-4 Load Balancing, USENIX NSDI, 2022.
- Yuanwei Lu, Guo Chen, Layong Luo, Kun Tan, Yongqiang Xiong, Xiaoliang Wang, Enhong Chen, One More Queue is Enough: Minimizing Flow Completion Time with Explicit Priority Notification, IEEE INFOCOM, 2017.
- Bojie Li, Kun Tan, Layong Luo, Yanqing Peng, Renqian Luo, Ningyi Xu, Yongqiang Xiong, Peng Cheng, Enhong Chen, ClickNP: Highly Flexible and High-performance Network Processing with Reconfigurable Hardware, ACM SIGCOMM, 2016.
- Guo Chen, Yuanwei Lu, Yuan Meng, Bojie Li, Kun Tan, Dan Pei, Peng Cheng, Layong Luo, Yongqiang Xiong, Xiaoliang Wang, Youjian Zhao, Fast and Cautious: Leveraging Multi-path Diversity for Transport Loss Recovery in Data Centers, USENIX ATC, 2016.
- Layong Luo, Gaogang Xie, Yingke Xie, Laurent Mathy, Kave Salamatian, A Hybrid Hardware Architecture for High-speed IP Lookups and Fast Route Updates, IEEE/ACM Transactions on Networking, 2014.
- Layong Luo, Gaogang Xie, Kave Salamatian, Steve Uhlig, Laurent Mathy, Yingke Xie, A Trie Merging Approach with Incremental Updates for Virtual Routers, IEEE INFOCOM, 2013.
- Layong Luo, Gaogang Xie, Steve Uhlig, Laurent Mathy, Kave Salamatian, Yingke Xie, Towards TCAM-based Scalable Virtual Routers, ACM CoNEXT, 2012.
- Layong Luo, Gaogang Xie, Yingke Xie, Laurent Mathy, Kave Salamatian, A Hybrid IP Lookup Architecture with Fast Updates, IEEE INFOCOM, 2012.